1. Field of the Invention
The present invention relates to a magnetic random access memory (MRAM) and, more particularly, to a bit line bias potential for a reference cell to be used when reading out stored information from a memory cell.
2. Description of the Related Art
The MRAM is a device that performs a memory operation by storing information “1” or “0” by using the magnetoresistive effect. The MRAM is regarded as a candidate for a universal memory device that is a highly integrated, highly reliable, low-power-consumption, nonvolatile device capable of a high-speed operation. Several manufacturers have begun developing MRAMs.
Many MRAMs using elements exhibiting the TMR (Tunneling Magneto Resistive) effect among other magnetoresistive effects have been reported. The TMR effect element has a stacked structure including an insulating film sandwiched between two metals as ferromagnetic layers. Generally, an MTJ (Magnetic Tunnel Junction) element using the change in magnetic resistance caused by the spin polarization tunnel effect is used as the TMR effect element.
More specifically, the MTJ element has the following resistance value. First, when the spin directions in the upper and lower ferromagnetic layers are parallel, the tunnel probability between the two magnetic layers sandwiching the tunnel insulating film is maximum, so the resistance value is minimum. On the other hand, when the spin directions in the upper and lower ferromagnetic layers are antiparallel, the tunnel probability is minimum, so the resistance value is maximum. To achieve these two spin states, the magnetization direction in one of the two magnetic films is normally fixed and set to be unaffected by external magnetization. This layer is generally called a pinned layer (fixed layer). The magnetization direction in the other magnetic film can be programmed to be parallel or antiparallel to that in the pinned layer in accordance with the direction of an applied magnetic field. This layer is generally called a free layer (recording layer), and has a function of storing information. The resistance change ratio (MR ratio) of the MTJ element is presently higher than 50%, and this high resistance change ratio directly ensures a large read margin. Accordingly, the TMR effect element is currently most frequently used in the development of the MRAM.
Data is read out from the MRAM using the MTJ element as follows. That is, a voltage is applied between the two magnetic layers of an MTJ element corresponding to a selected bit line, and the resistance value is read from an electric current flowing through this MTJ element. Alternatively, a constant current is supplied to a selected MTJ element, and a voltage generated between the two magnetic layers by this electric current is read out.
On the other hand, data is written in the MRAM using the MTJ element as follows. To reverse the magnetization direction in the free layer of the MTJ element, electric currents having a value equal to or larger than a predetermined value are supplied to a bit line and word line perpendicularly crossing a memory cell. The magnetization direction in the free layer is programmed by the magnitude of a synthetic magnetic field generated by the electric currents.
Non-patent reference 1 or the like is reported as an example of the MRAM using the MTJ element. A read circuit disclosed in non-patent reference 1 uses a reference cell having a pair of MTJ elements set in a low-resistance state and high-resistance state, in order to generate a reference signal to be input to a sense amplifier. A constant voltage is applied to these two MTJ elements, and electric currents flowing through the MTJ elements are added by a current mirror circuit and divided by 2, thereby generating a desired signal current.
By contrast, patent references 1 and 2 have proposed a method in which an MTJ element in the low-resistance state is used as a reference cell, a bit line clamp voltage for this reference cell is read out, and a potential different from this bit line clamp voltage is applied to a bit line clamp voltage for a memory cell, thereby generating a desired signal current. Since the method can reduce the number of reference cells in an array by half, the effect of reducing the chip size can be expected. Therefore, the method is optimum for high integration.
Unfortunately, the read methods disclosed in patent references 1 and 2 have the following problems.
As shown in FIG. 1 of patent references 1 and 2, an operational amplifier 35 and transistor 32 apply a potential VBIAS1 to a read cell 17 in a read operation. On the other hand, an operational amplifier 45 and transistor 42 apply VBIASREF different from that of the read cell 17 to a reference cell 27. A reference voltage generator shown in FIG. 3 of patent references 1 and 2 generates VBIASREF. In FIG. 3 of patent references 1 and 2, an MTJ element in a memory cell 60 is set in a low-resistance state Rmin, an MTJ element in a memory cell 62 is set in a high-resistance state Rmax, and VBIAS/2 that is ½ the bias potential of the read cell is applied to the positive input terminal of an operational amplifier 56, thereby generating VBIASREF given byVBIASREF=(VBIAS/2)×(1+Rmin/Rmax)  (1)
When the potential VBIASREF given by equation (1) above is applied to the operational amplifier 45 shown in FIG. 1 of patent references 1 and 2, an electric current IREF flowing through the reference cell 27 set in the low-resistance state is given byIREF=(VBIAS/2)×(1/Rmin+1/Rmax)  (2)
Assuming a read cell to which VBIAS is applied, the electric current IREF is ½ a signal current flowing through cells in the low-resistance state Rmin and high-resistance state Rmax, and hence is desirable as a reference signal. Accordingly, a signal voltage corresponding to read cell information is read out as VO and VOREF as the output potentials of a read-system circuit shown in FIG. 1 of patent references 1 and 2.
As indicated by equation (1), the potential generated by the reference potential generator shown in FIG. 3 of patent references 1 and 2 is expressed by only VBIAS/2 as the input potential to the operational amplifier 56 and the resistance values Rmin and Rmax of the MTJ elements having two different resistance values. The absolute resistance value of the MTJ element generally depends on bias. Qualitatively, the resistance value decreases as the voltage applied across the two terminals of the MTJ element increases.
When the bias dependence of the MTJ element as described above is taken into consideration, since the potential VBIAS/2 is applied to the MTJ element of the memory cell 62 to be set in the high-resistance state Rmax, the resistance is actually Rmax−ΔRmax, i.e., decreases. In addition, since a potential equal to or lower than VBIAS/2 is always applied to the MTJ element of the memory cell 60 to be set in the low-resistance state Rmin, the resistance is Rmin−ΔRmin, i.e., decreases. In this case, the potential VBIASREF produces an error at a predetermined value from a desired voltage. This means the fluctuation of the reference cell signal, and deteriorates the read margin.
[Non-patent reference 1] 2004 Symposium on VLSI Circuits Digest of Technical Paper, pp. 454-457, “16 Mb MRAM Featuring Bootstrap Write Driver”
[Non-patent reference 2] IEEE International Device Meeting 2005, “High Speed Toggle MRAM with MgO-Based Tunnel Junctions”
[Patent reference 1] U.S. Pat. No. 6,385,109
[Patent reference 2] U.S. Pat. No. 6,496,436